1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory equipment operative in an asynchronous refresh mode for data processing systems. In particular, the invention concerns a control circuit used in such memory equipment.
2. Description of the Prior Art
In general, the dynamic type semiconductor memory element is adapted to store information in terms of the presence and absence of electric charge. Because the electric charge is progressively discharged due to unavoidable leakage in the circuitry of the memory element, a refreshing operation is required for supplementing the lost charge within a predetermined time. Such a refresh operation may be effected in two different modes. In the first mode, referred to as the synchronous refresh mode, a refresh command signal is periodically issued to the memory equipments from an external unit such as, for example, a central processing unit, hereinafter referred to as a CPU, thereby to effect periodically the refershing operation in all the memory devices or equipments. On the other hand, in the second refresh mode, which is referred to as asynchronous refresh mode, a refresh request circuit is inherently incorporated in each of the memory equipments, whereby the refreshing operation for the memory elements of any given memory equipment is spontaneously effected in response to the refresh request signal independently from the other memory equipments.
In the hitherto known dynamic type semiconductor memory equipment operative in the asynchronous refresh mode, when the refresh operation is initiated in a memory equipment, a signal indicating that the memory equipment is in operation (this signal will be hereinafter referred to also as the busy signal) is produced and sent to an external unit such as a central processing unit for inhibiting the access request therefrom to the memory equipment in the busy state. When a plurality of the memory equipments are provided, the busy signal lines from the various memory equipments are usually combined into a single common bus connected to the CPU. Accordingly, when the refresh operation is effected in one of the semiconductor memory equipments, resulting in the busy signal being sent to the busy signal bus common to all the memory equipments, the CPU is inhibited from making access to the other memory equipments and has to wait until the refreshing operation being effected has been completed. In an extreme case in which all the memory equipments successively perform the refresh operations in sequence, a remarkably great time is required in vain before the access request to any one of the memory equipments is allowed from the CPU, since the latter has to wait until the refresh operations in all the memory equipments have been completed. This means a significant reduction in the otherwise available capability of the CPU.